- Chapter 1
- Lesson 1: Evolution Computers Part 1: Mechanical Systems, Babbage method of Finite Difference Engine and Turing Hypothesis
- Lesson 2: Evolution of Computers Part 2- First generation Computers
- Lesson 3: Evolution of Computers Part 3- Second generation computers Computers
- Lesson 4: Evolution of Computers Part 4- Third generation computers
- Lesson 5: Evolution of Computers Part 5- Fourth generation computers
- Lesson 6: Technological Trends, Measuring and Improving Performance
- Lesson 7: Introduction to Computer Architecture
- Chapter 2
- Lesson 1: Von Neumann Machine Architecture
- Lesson 2: Functional units and components in a computer organization- Part 1: Processor
- Lesson 3: Computer Organisation
- Lesson 4: Computer Organisation
- Lesson 5: Functional units and components in a computer organization Part 4- ALU
- Lesson 5: Computer Organisation
- Lesson 6: Program development process and tools
- Lesson 7: Program development process and tools
- Lesson 8: Operating Systems
- Lesson 9: Computer Organisation
- Chapter 3
- Lesson 1: Representations of Positive and Negative Integers
- Lesson 2: Arithmetic Operations- Addition and subtraction
- Lesson 3: Arithmetic Operations- Adder and Subtractor circuits Design
- Lesson 4: Arithmetic Operations- Multiplication of Integer numbers
- Lesson 5: Arithmetic Multiplication Circuits
- Lesson 7: Integer Division
- Lesson 8: Floating-Point Numbers (IEEE754 Standard) and Operations
- Lesson 9: Arithmetic using floating point numbers
- Lesson 10: BCD Arithmetic Operations, Packed Decimals and Unpacked Decimals
- Lesson 11: Design of ALU
- Chapter 4
- Lesson 1: General-Purpose Register Organization
- Lesson 2: Register transfers
- Lesson 3: Basic operations and Instruction Formats
- Lesson 4: Type of Operands in the instructions
- Lesson 5: Basic Addressing Modes for operands
- Lesson 6: Accessing the operands
- Lesson 7: Instruction Set Features
- Lesson 8: Processor Instructions - Part 1
- Lesson 9: Processor Instructions - Part 2
- Lesson 10: Processor Instructions - Part 3
- Lesson 11: Generation of Memory Addresses and Addressing Modes
- Lesson 12: Instruction Set of a GPRs based processor
- Lesson 13: Subroutine Nesting Using Stacks to Implement Subroutine Calls
- Lesson 14: Use of the Stack Frames
- Lesson 15: Stacks Addressing
- Lesson 16: Queues Addressing
- Lesson 17: Encoding of Instructions
- Lesson 18: Stack-based processor Organisation
- Lesson 19: CISC Architectures
- Lesson 20: RISC and converged Architecture
- Chapter 5
- Lesson 1: Basic Processing Units
- Lesson 2: Bus Architecture
- Lesson 3: Register transfers
- Lesson 4: Bus, register and Memory transfer for data path implementation
- Lesson 5: Instruction fetch in a data path implementation
- Lesson 6: Performing an Arithmetic or Logical Operation
- Lesson 7: Microoperations for Shifts or rotate
- Lesson 8: Fetch a Word from Memory and Transfer to IR or GPR or other Word Storing Unit
- Lesson 9: Execution of complete instruction
- Lesson 10: Execution of a branch instruction
- Lesson 11: Multiple Bus Organisation
- Lesson 12: Sequencing of Control Signals
- Lesson 13: Hardwired control
- Lesson 14: Microprogrammed Control
- Lesson 15: Microinstructions
- Lesson 16: Horizontal and Vertical organisation of Microinstructions
- Lesson 17: Microprogram sequencing and next address field
- Lesson 18: Nanoprogramming
- Lesson 19: Control memories in Bit Slice Processor
- Chapter 6
- Lesson 1: Instruction Pipeline
- Lesson 2: Pipeline Performance
- Lesson 3: Instruction Hazards and Data hazards
- Lesson 4: Control Hazards and Branches
- Lesson 5: Structure hazards and Score boarding
- Lesson 7: Overcoming Hazard by Result Forwarding (Bypassing)
- Lesson 8: Instruction Set Design Influence on Pipelining
- Lesson 9: Superscalar Processors and Parallel Computer Systems
- Lesson 10: In-order execution
- Lesson 11: Reservation station, Register Renaming Technique and dynamic scheduling on registers
- Lesson 12: Out-of-order execution
- Lesson 13: Dynamic Hardware Branch Prediction
- Lesson 14: Example of the Pipelined CISC and RISC Processors
- Lesson 14: Example of the Pipelined CISC and RISC Processors
- Lesson 1: General Features of RISC and CISC
- Lesson 11: Register Renaming Technique
- Chapter 7
- Lesson 1: Instruction: Level Parallelism in Superscalar Processors and Parallel Computer Systems
- Lesson 2: Pipeline level and higher level Parallelism Concepts in Parallel Processing
- Lesson 3: VLIW Processor: Pros and Cons of VLIW
- Lesson 4: Vector Processors
- Lesson 5: Array Processors
- Lesson 6: Multithreaded Processors
- Lesson 7: Multi-core Processors
- Lesson 7: Compilation Techniques and Support to Instruction Level Parallelism
- Chapter 8
- Lesson 1: Basic Concepts
- Lesson 2: Memory Hierarchy
- Lesson 3: Hit Rate, Miss Rate and Computing Average Access Time
- Lesson 4: Replacement, Inclusion, Write-back and write- through policies
- Lesson 5: SRAM and DRAM Memory chips and their internal Organisation
- Lesson 6: Asynchronous Dynamic RAMs (DRAMs) and Access cycles and access time in Asynchronous DRAM in normal mode
- Lesson 7: Page mode and fast-page mode DRAMs
- Lesson 8: Synchronous DRAM (SDRAM) and DDR-SDRAM
- Lesson 9: DRAM access controller and Refresh Logic Control
- Lesson 10: Memory Access Cycle Time, Latency, Throughput, and Bandwidth
- Lesson 11: Memory Banking
- Lesson 12: Memory Interleaving
- Lesson 13: Precharging and replication
- Lesson 14: Memory Storage Error Correction
- Lesson 15: Semiconductor Read-Only Memories-ROMS
- Lesson 16: Memory speed, size and cost
- Lesson 17: Auxiliary memory Peripheral Devices - Secondary Storage Magnetic Ferrite Core Memories
- Lesson 18: Peripheral devices for memory- Optical Disks CDROM Memories
- Lesson 19: Secondary storage - RAID
- Chapter 9
- Lesson 1: Cache and its Access
- Lesson 2: Cache Access and basic Features
- Lesson 3: Cache Associativity
- Lesson 4: Replacement policy
- Lesson 5: Write through and write back policy
- Lesson 6: Cache Implementation
- Lesson 7: Cache Implementation
- Chapter 10
- Lesson 1: Virtual memory organisation
- Lesson 2: Address mapping and translation
- Lesson 3: Page tables and address translation process using page tables
- Lesson 4: Associative Memory [Content Addressable Memory (CAM)] and Page Replacement policy
- Lesson 5: Translation Lookaside Buffers
- Lesson 6: Partitioning and Multilevel Page tables
- Lesson 7: Segmentation and Partitioning of virtual address space into segment and page addresses
- Lesson 8: Demand Paging and Page Swapping
- Lesson 9: Caches and Virtual Memory
- Chapter 11
- Lesson 1: Input-Output devices (Peripheral devices) and IO organisation
- Lesson 2: Accessing the I/O devices and Interface circuit
- Lesson 3: Synchronous data transfer
- Lesson 4: Asynchronous data transfer
- Lesson 7: Interrupts- Part 1
- Lesson 8: Interrupts- Part 2
- Lesson 10: Direct Memory Access (DMA)
- Lesson 11: Input-Output Processor
- Lesson 12: Bus Arbitration
- Lesson 13: Parallel Port
- Lesson 14: Serial Port
- Lesson 15: Standard I/O bus- PCI
- Lesson 16: Standard I/O bus- SCSI
- Lesson 17: Standard I/O buses- USB (Universal Serial Bus) and IEEE1394 FireWire Buses
- Lesson 18: Peripheral Devices- Keyboard, Mice, touch screen and light-pen
- Lesson 19: Peripheral Devices- Printer Devices
- Lesson 20: Peripheral Devices- Display Devices
- Chapter 12
- Lesson 1: Performance characteristics of Multiprocessor Architectures and Speedup
- Lesson 2: Flynn Classification of parallel processing architectures
- Lesson 3: Multiprocessor System Interconnects- Hierarchical Bus and Time Shared bus Systems and multi-port memory
- Lesson 4: Interconnect Networks
- Lesson 5: Shared Memory Systems- Memory Organization in Multiprocessors
- Lesson 6: Centralized Shared Memory Architecture
- Lesson 7: Distributed Shared Memory Systems
- Lesson 8: Bus Shared Memory Systems
- Lesson 9: Cache Coherence Problem and Cache synchronization solutions- Part 1
- Lesson 10: Cache Coherence Problem and Cache synchronization solutions- Part 2
- Lesson 11: Hardware synchronization mechanisms
- Lesson 12: Message passing Systems and Comparison of Message Passing and Sharing
- Lesson 13: Deadlock and virtual channels, and Flow control strategies
- Lesson 14: Cluster Computing and issues in Cluster Computing